When simulating the interconnection of computer chips including Application Specific Integrated Chips (ASICs), it has been common in the prior art to employ Hardware Design Languages (HDL) to implement Register Transfer Logic (RTL) for simulating various devices. Generally, HDL is employed to simulate the operation of individual chips as well as to interconnect the chips for simulation operations.
Generally, implementation of the chip and interconnection in HDL is highly demanding of both computer memory and execution time causing simulation of large systems employing HDL may be very slow to compile and execute. Since computational resources and time may be limited, the slowness of compilation and execution of system designs employing HDL may prevent complete system testing from being accomplished. On occasion, short-cuts may be employed, such as executing a compilation employing only a subset of a particular chip. Such short-cuts may compromise the quality and accuracy of simulation of an overall system.
Because of the demands upon time and computational resources of HDL simulation, system simulations are generally limited to the most common sequences of operation of the chips and the overall system being simulated, thereby commonly preventing simulation of xe2x80x9cdeep cornerxe2x80x9d cases, or less common system conditions. Simulation under such conditions may produce an incomplete picture of system operation.
Due to the nature of HDL coding and simulation, modifying a set of interconnections between chips in a system generally requires that a programmer spend a considerable amount of time modifying the system configuration in HDL. Once the changes to HDL code have been input, substantial time will then generally be spent recompiling the modified HDL system representation. The time required for system redesign and recompilation when employing HDL generally discourages testing a substantial range of system configurations, thereby making the HDL approach to simulation a relatively static one.
Therefore, it is a problem in the art that HDL simulation is very computationally demanding.
It is a further problem in the art that extensive redesign and recompilation time is required to modify a system configuration when employing HDL.
It is a still further problem in the art that the extensive demands of HDL simulation generally restricts the amount of system testing and the variation in system configurations likely to be tested when employing HDL simulation.
These and other objects, features and technical advantages are achieved by a system and method which operates to insert high level language (HLL) interfaces in between RTL simulations of ASICs or other chips and optionally HLL emulations of selected ASICs to enable rapid and dynamic system reconfiguration employing a HLL. The substitution of high level language code (such as, for instance, xe2x80x9cCxe2x80x9d language code) for RTL interconnection logic preferably operates to permit a programmer to use a more convenient and flexible mechanism to reconfigure a system for subsequent simulation.
In selected instances, HLL code may be employed to emulate an entire chip, particularly where an RTL simulation for a particular chip does not already exist. Generally, HLL emulation is more rapid and flexible to implement but somewhat less accurate than RTL simulation of the same chip. However, HLL implementation of interconnection of the RTL-simulated ASICs (or other circuit devices) is generally as accurate as RTL implementation of the same interconnection. In a preferred embodiment, by employing RTL code for simulating individual ASICs, and HLL code for flexibly interconnecting the RTL simulated ASICs, improved simulation flexibility and execution speed may be obtained while preserving simulation accuracy.
A system and method for building and connecting the various HLL and RTL components of a configuration is also provided. For a given set of nodes in a configuration, dynamic configuration code is provided which preferably builds each node in the configuration according to a specification for that node. The dynamic configuration code then preferably follows links from the built node to neighboring nodes to identify remaining unbuilt nodes in the configuration and build nodes as needed. This process preferably continues until all nodes in the configuration have been built. The dynamic configuration code also preferably copies interface pointers for each node as needed in order to ensure that data may be effectively routed through the configuration.
Therefore, it is an advantage of a preferred embodiment of the present invention that interconnections between chips in a system under simulation testing may be readily, flexibly, and rapidly modified.
It is a further advantage of a preferred embodiment of the present invention that more rapid simulation of systems may enable a greater of number of situations to be tested for a particular system configuration.
It is a still further advantage of a preferred embodiment of the present invention that more rapid simulation of systems may enable a greater number of system configurations to be tested before a system is scheduled for fabrication.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.